![]() ![]() ![]() Both languages support connectivity by position, which can lead to mismatches. Analog (circuit) tools use SPICE and don t necessarily use vectors. Solution: Remove assigns during init_design: set init_remove_assigns 1 Just to make sure, remove assigns again after placement: delete_assigns -add_buffer a assign b = a b 12ġ2 Problem #3: Bus Notation Issue: Verilog uses square brackets for vectors my_memory memory (.dout(my_signal)) But Virtuoso uses triangular brackets dout my_signal In the year 2020, this can still confuse the EDA tools Solution: When exporting your CDL from Virtuoso, select Map Bus Names from to 13ġ3 Problem #4: Flipped Busses Issue: Digital tools use Verilog and often consider busses as multi-bit vectors. v2lvs will convert some assigns into *.connect commands, but LVS will sometimes fail, for example, an assign connecting two inputs. ![]() Synthesis should get rid of them, but it doesn t always. But many Gatelevel tools, don t like these assigns. ![]() Digital-on-Top LVS Custom (Virtuoso) LVS Flow Digital-on-Top (Innovus) LVS Flow Source Netlist Layout Netlist write_netlist write_stream = Verilog Netlist GDSII Why is the digital-on-top flow problematic? v2lvs extract Because of the integration of IP and hierarchical blocks! = 6 Source Netlist Layout September Adam Teman, Netlist 27, 2020Ħ The complete digital-on-top LVS .cdl v2lvs Verilog Netlist Source Netlist = LVS extract.gds GDSII binary Layout Netlist ERC Report 7ħ So let s make it simple Before going into the problematic details, let s assume everything is fine: Write out Verilog netlist from Innovus write_netlist -phys -exclude_leaf_cells -flatten_bus my_module.v Run v2lvs to create the Source SPICE netlist v2lvs -sn -v my_verilog.v -o my_output_cdl.cdl -s my_includes_file.sp Write out GDSII from Innovus write_stream my_layout.gds -merge $ALL_GDS -map_file $mapfile -unit 1000 Extract Layout SPICE netlist from GDSII calibre -hier -64 -hyper -turbo -spice my_layout_netlist.sp runset.extract Compare Source and Layout Netlists calibre -hier -64 -turbo -hcell heclls.txt pare Now let s look at all those painful details 8Ĩ Introduction Verilog Netlist V2LVS Extraction LVS DRC Creating the LVS-ready Verilog Netlist 9ĩ Writing out the Verilog Netlist Basic command: write_netlist -phys -exclude_leaf_cells my_module.v But many problems: Global Net connectivity Bus Notation Assigns Flipped Busses Excluded Instances Excluded Hierarchical Blocks write_netlist Verilog Netlist 10ġ0 Problem #1: Missing Global Nets 11 Issue: Logical connectivity (GTL netlist) doesn t require power nets CMOS gates assume the existence of a logic 1 and a logic 0 But these logic levels may come from different voltage sources Solution: The write_netlist phys flag writes out global power nets However, you first need to initialize these in CPF/UPF or init_design: set_db init_ground_nets set_db init_power_nets And you need to connect them to the right pins connect_global_net To verify the connections, use the design browserġ1 Problem #2: Assigns in your Netlist Issue: RTL uses the assign keyword in Verilog quite frequently. ![]()
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